Dynamic hardware logic and in particular that one of the domino type allows very complex logic functions to be implemented, as only NFET transistors realize the logic function. The P-FET part is only used to precharge the circuitry. Thus, in such circuitry a logic function is usually implemented between a node precharged to a higher voltage potential of said circuit, for example a supply voltage, herein abbreviated as Vdd, and a lower potential, for example ground, which function processes a plurality of input variables A, B, C, . . . . Such circuit is usually implemented in some single combinatorial switching arrangement, i.e. a net of transistors, which are arranged in a particular way including parallel and/or serial connections between Vdd and ground potential.
Generally, for example when implemented in dynamic MOS logic, special care has to be taken to hold the above-mentioned precharged node on its defined level as to voltage potential, as amongst others the effect of “leakage” and “charge sharing” tend to reduce the voltage level at this precharged node, which can lead to malfunction. In short words, charge sharing means that the charge which has been entered into the precharged node flows away into the capacities built up by the next transistors connected next to the node in direction to ground. In particular in such cases, in which a stack of transistors connected in series or connected in parallel are switched on, a considerable charge quantity flows into the capacities of these transistors, which may lead to a respective considerable voltage drop at the precharge node. This may lead to malfunction of the logic.
With reference to FIG. 1 in prior art it is known to apply so-called “keeper-devices” and/or “bleeder-devices” which try to supply charge to the precharge node temporarily or continuously, respectively. This reduces the charge sharing effect, but also slows down the switching of the circuit. Keeper and bleeder devices charge the node 10, which works against and slows down the discharge of this node in case the logical function forces a discharge of node 10.
This problem will be better understood by the description next below: in FIG. 1 the node 10 denoted as “pre_1” is the above-mentioned precharge node. During the so-called reset phase it is precharged to a certain voltage level, e.g. the supply voltage Vdd. This is done by the control of the reset transistor 12 which when switched to “pass” connects the precharge node to the voltage source Vdd.
A “half latch” 22 surrounded by broken lines comprises an inverter 21, the output of which is connected to the gate of transistor 20, which connects the supply voltage with the precharge node when it is opened by the inverter 21. This transistor 20 acts as a keeper device provided for keeping the voltage high in case the precharge node looses some charge to transistors 13 or 14.
During the evaluation phase of the circuit, when some input setting is connected to the control inputs of the NFETs 13, 14, 15, the transistors remove this charge to ground, if the logic condition as defined by the value of the logic input variables A, B, C, turns “ON”, i.e., to pass mode, all transistors on the path depicted between the precharged node 10 and ground terminal 16. If only a part of said transistors are turned “ON” without opening up a connection between the precharged node and ground, then the node has to keep its charge. When, for example transistors 13 and 14 are switched to pass mode then the precharge node 10 must share its charge with those active transistors 13, 14. Thus, basically the keeper device 20, which was already mentioned above and is depicted in the right top portion of FIG. 1 is used in prior art in an enlarged dimension in order to compensate the charge sharing and keeping the voltage high at the precharge node.
An increased keeper device, however, increases disadvantageously the lump capacitance of the precharge node 10 and decreases the switching performance during the evaluation phase.
A further approach to reduce the problematic effects of charge sharing in such dynamic logic gates is disclosed in U.S. Pat. No. 5,317,204 assigned to Hewlett Packard Company. In this patent it is disclosed to reduce the interstitial space between parallel transistor gates in order to minimize such parasitic capacitance. Further, it is disclosed to dispose transistor gates adjacent to one another in order to let the transistors share a common interstitial space with a region of each transistor gate adjacent a region of each of the other remaining gates.
These measures, however, are not yet sufficient in particular for circuits which comprise more complex logic functions with an increased amount of transistors (e.g. 8 or more) or longer stacks of transistors, as for example a path comprising a number of 5 to 8 transistors switched in series.